PCB vias – Which to choose and how they affect BGA fanout and layer count

Vias are one of the basic building blocks of any modern PCB design. Whenever we have more than one copper layer, vias are the structures that transfer a signal from one layer to another. Consider the simplest case – we have a PCB substrate (FR-4) with a top and bottom copper layer. If a signal wants to hop from one layer to the other, it will do that through a via.

Vias for thermal management

Since copper is good thermal conductor, besides electrical connectivity, vias are used for thermal connectivity also – the idea is to decrease the thermal resistance from the heat source (soldered power component) to a large copper surface. We can do that via larger via stitching regions (called thermal vias in this case), as we’ve discussed in the previous blog about thermal management written by my colleague Milan.

Basic parameters of vias

Hole size

The hole's diameter (typically 0.2–0.5 mm). If we need to go smaller, we need to use micro-vias (laser drilled, more on that later).

Diameter

The diameter of the complete via pad (on top and bottom layer).

Annular ring

The metallization ring that remains after the drilling of the PCB. In an ideal world (and in CAD tool), the double annular ring is the dimension you get when you subtract the diameter of the hole from the via diameter. This is the usual parameter specified by the PCB fab in their capabilities brochure. Why is it important – because the copper layers will have the misregistration between themselves. If the annular ring is too small, it might not exist on a certain layer(s) due to misregistration.

Types of vias

Tented vias

Tenting means simply letting the solder mask covering the via hole. This is an indeterministic process, as solder mask can cover a complete hole in some cases, while it will leave part of the hole in the other. So, we can’t rely on it for anything. If the hole is completely covered, the air pocket will be kept inside. During the reflow process, this air will expand to the point of a mini explosion and possibly cause a defect.

Plugged vias

“Plugging” means filling vias with an epoxy or other non-conductive low-viscosity material. Since epoxy is not a much better thermal conductor than the air, this provides no benefit in thermal conductivity but protects for the metallization inside of the via barrel.

Filled vias

Vias that are filled with a conductive material, most often epoxy resin mixed with a metal (gold, silver, copper, aluminum, tin or a combination). This results in a price increase but makes vias a much better electrical and thermal conductor.

Via in pad

To be able to locate vias in the middle of the component pads, they must be filled (in any way) and their surface plated to create a uniform surface. Of course, this also increases the price, so if we want to keep it to a minimum, we’ll keep vias away from the pads.

Expanding to multi-layer PCB design

So far, we’ve discussed simple TH vias used in a two-layer PCBs. By expanding the picture to a multi-layer PCB, we get a few additional options.

Micro-vias

Laser drilled vias with a hole diameter of 0.15 mm or smaller. This can be done only through thin substrates (prepregs), as micro-via needs to have an aspect ratio of preferably 0.75:1 (and maximum of 1:1). Aspect ratio is defined as via height divided by via width. Since micro-vias start at 0.15 mm (and can only get smaller), this means the maximum substrate thickness should be 0.15 mm. If we have micro-vias in our design, we are talking about HDI (high-density interconnect) technology.

Blind/buried vias

These are types of micro-vias. Micro-vias that go from the outer to an inner layer are called blind vias. The ones that go from one to the other inner layer are called buried vias.

Core vias

Like through-hole vias, but don’t go through a complete PCB stackup. Instead, mechanical drilling is performed on the central stack of layers before the rest of the lamination cycles. This is important since laser drilling can’t be performed through the core of the PCB (due to the thickness), only through the prepregs.

Choosing the right via for your PCB design

Once we add micro-vias to the design, with each new drill pair (pair of layers interconnected with via) we add two additional steps to a PCB fabrication process (drilling and plating of micro-vias). This, of course, increases the price. Keeping the number of PCB fabrication steps to a minimum, as well as the technology requirements, results in a PCB with:

• The highest reliability,
• Easier debugging and reworking in prototyping phase,
• Lower price.

How to choose the right via technology?

As we’ve seen so far, there are plenty of technological options to implement vias, so how do we choose which option to go with? The technology choice is one of the first tasks while starting the PCB layout of your design, as we need to know what tools we have at our disposal during the layout. The parameters that will affect this decision are most likely:

• The most complex component package in the design,
• The number of signals that need to be fanned out,
• The number of copper layers on the PCB.

Examples to illustrate via selection

Let me illustrate this through a couple of examples.

0.8 mm pitch BGA package fanout – no HDI

This is a large pitch package, so we can get away without using via in pad by locating vias in space between pads. Also, it is possible to fan out all signals by using only through hole vias (0.4 mm diameter, 0.2 mm hole). This combo (large pitch BGA package and TH vias) means we can fan out two rows of the signals on a top (red) layer without any vias. The next two rows require vias and one additional (gold) layer. After that, each additional row requires one routing layer. So, the number of signals we need to fan out dictates the number of copper layers. The solution presented in this discussion has 289 fanned out signals. The minimum clearance used in the solution below is 0.15 mm (6 mils) and minimum width of the copper traces is 0.1 mm (4 mils), which is not an exotic thing.

In the figure above, you can see all vias are placed in the locations between the BGA package pads. The package is virtually divided into four segments - see top (red) layer, the direction of breaking vias. This enables us to place the decoupling capacitors in the cross shape on bottom (dark blue) layer and connect through vias to the power planes. In the above figure, power pins are neglected, and component is handled as if all pins are signals, just to illustrate the fanout method.

The advantage of this type of design is that it does not utilize any of the HDI technologies – we have plain TH vias (no micro-vias), only one drilling layer pair (all vias are drilled from top to bottom) and no via in pad. The only drawback is potentially the higher number of copper layers. Note that you cannot use six layers for routing on a 6-layer PCB, as you need to accommodate reference planes for high-speed signals. For this, you’d probably want at least a 10-layer board – but we’ll leave this topic for another discussion.

0.8 mm pitch BGA package fanout – with HDI

Another way to tackle fanning out the large number of signals from BGA package is by using the HDI artillery - the blind and buried vias (i.e. multiple drill pairs) and smaller width and copper clearance (0.1 mm). The approach is shown in the figure below.

This allows us to route two traces through spaces between vias. The first three rows would be fanned out on the top (red) layer. Once we fill all the spaces on the top layer, we switch to the first internal signal layer. Here, we have smaller vias and again, we can route two traces in the space between them. Each new layer has a clean start since we use blind vias. We can see that by introducing a blind vias, we can do a BGA fanout much easier and by using fewer copper layers. Of course, the drawback is a PCB with much stricter technological requirements – less copper width and clearance, laser drilling (micro-vias) and blind vias. This makes PCB harder to fabricate and adds multiple additional steps to its fabrication.

Comparison

By comparing the two approaches mentioned above, we can see there is a trade-off between increasing the number of copper layers (but otherwise keeping technology requirements lower) and adding the HDI technology (blind vias and more steps in the PCB fabrication process). The decision on which approach to take might be dictated by the rest of the system design (maybe some other component will require having a blind via or a higher number of copper layers). If there is no other part of the system that would indicate this, a good call is to discuss this with the preferred PCB fab. Common agreement with the design house and PCB fab would result in a design that is the easiest to manufacture given the application requirements (meaning the cheapest possible, of course).

0.5 mm pitch BGA Package Fanout

This is a slightly more demanding package (technology-wise). Depending on the number of required signals, we might get away with TH vias in some cases. In other, we’ll need to use blind vias, but more on that in a bit. First, we need the via-in-pad capability, as there is no space to place vias between pads.

In some cases, where the number of signals is not very high (e.g. eMMC memories), we can take advantage of a couple of facts:

• The package can have many solder balls, but with a very low percentage of them used in the application. Most of them are not connected internally (you need to be careful here for multiple reasons, though). Reason number one – through the lifetime of your product, you will most certainly want to change the memory supplier (in case of a component end of life or simply a better price from a new supplier). Although the pinouts are typically standard, some “not connected” balls could be used for internal testing in the factories by some memory manufacturers. Reason number two – although the memory datasheet says that some balls are “not connected”, this just means they shouldn’t be connected in the actual application (not that they are not connected internally in the chip).
• The chip manufacturers tend to do a chip pinout in a way that needed pins are easily accessible. This means they will be either in the outer rows or located in not more than two consecutive rows. We will discuss why this is important.

In the figure below, we can see why these two facts are useful.

Note the ball C1 – “not connected” according to the memory documentation. We assign MMC_VDDI net to it and use it to route MMC_VDDI on the top (red) layer. The same goes for ball D4 (originally not connected on the package) – we used it to route out GND net. The second point – note the eight-bit data bus (located in rows A and B). Since we have no more than two rows of vias, we can route all signals out using TH vias.

To summarize, we can make a fanout using via-in-pad with TH vias, 0.1 mm (4 mils) electrical clearance and at least a two-layer PCB. This is very good from the perspective of cost optimization; however, we need to be very careful with the two-layer PCB design to keep EMI at the minimum and keep the signal integrity.

0.5 mm pitch BGA package fanout – MCU baseline

When it comes to microcontrollers, a much larger number of pins is utilized. Luckily, the pins that always must be employed on an MCU are typically located at easily accessible locations. Reference the figure below – a typical STM32 microcontroller in a 132-ball BGA package (0.5 mm pitch) with all mandatory peripherals (assuming we want to use external high-speed and low-speed crystals), like crystals, power decoupling, reset capacitor, boot pin configuration and SWD interface pinned out.

We can see this baseline can be implemented on a two-layer PCB with 0.1 mm clearance and TH vias (0.2/0.4 mm). Now, depending on your pin count needs, you have several possible directions:

• Using the same TH vias, fan out the necessary signals from the available MCU pins. Priorities while choosing the MCU pinout should be outer package rows (can be routed out without vias) or inner rows, but following the guidelines mentioned above (recall the memory fanout). This way you could easily get approximately 50 GPIO pins from the MCU and you would most likely have to settle with a four-layer PCB at least (to accommodate reference planes, signal and power routing). This is a cost-optimized solution that will be able to support you with a couple of dozens of MCU pins, which is not a small thing. Too rarely in practice, this approach is seen as PCB designers proceed with blind vias and a multi-layer PCBs as soon as they place that BGA in the design (when reality is, this can be drastically optimized for manufacturability and reliability, therefore price).
• If needed MCU pin count is higher than in the above case, you can easily do a fanout by introducing multiple blind vias (as in the case of a 0.8 mm pitch package) and a higher PCB layer count. Just for reference, this MCU package has 105 available GPIO pins (not including SWD and boot pins).

0.4 mm pitch BGA package fanout

Due to the extremely low pitch of the package, via-in-pad is a “must-have”. Further, to keep at least 0.1-0.15 mm clearance, you’ll want to use 0.25-0.3 mm via diameter. This means micro-vias need to be used.

Regarding the fanout, we have no other option but to work our way from the outer towards the inner rows of the package. We start with the outer rows, which are routed away on the surface layer. The next row gets blind vias that go to the first inner routing layer and so on.

What you need to be careful about – since micro-vias need to keep their aspect ratio (I believe you remember this from the beginning of the discussion), you’ll need to keep the dielectric thickness up to 0.15 mm. For PCB thickness of 1.6 mm, this can be hard (or impossible) for PCBs below 8 layers. Anyhow, just keep in mind to keep the dielectric thickness low and you’ll be fine. :)

Conclusion

PCB technology requirements are something you should be discussing with your fab at the beginning of the system design, i.e. while choosing the main components). Very often, the choice of the most complex component in the system will dictate the required PCB technology. If you are not in sync with your preferred PCB fab and it turns out it can’t meet these requirements, this is something that could present the showstopper. Otherwise, working together with the PCB fab on these crucial decisions would yield a reliable and a manufacturable result.

For more information on PCB vias – Which to choose and how they affect BGA fanout and layer count talk to ESCATEC Mechatronics Ltd